Patent Literature 1 shows a memory interface control circuit in which a data strobe signal provided from a DDR2-SDRAM (Double Data Rate 2 Synchronous Dynamic Random Access Memory) is delayed by a variable delay circuit to adjust the timing to latch data provided from the DDR2-SDRAM.
Patent Literature 2 shows training an asynchronous ODT (On-Die Termination, termination resistance). It also shows a memory module including a plurality of memory ranks.
The entire disclosures of the above mentioned Patent Literatures are incorporated herein by reference thereto. The following analysis is given by the present invention.
In a memory system including a memory module, having a plurality of memory ranks, and a control device, such as a memory controller, the control device determines a shift value of a data strobe signal for a plurality of memory devices belonging to the same rank group, that is, a plurality of memory devices whose data terminals as well as data strobe terminals are connected in common. In determining the shift value of the data strobe signal, training is carried out for just one of the plurality of memory devices of the same rank group.
However, in such method, the delay value in forwarding between the control device and a plurality of memory devices in the rank group cannot be represented accurately. Therefore, there is a risk that the margin in receiving data by the control device tends to be decreased.
Patent Literature 1 shows that, in case a plurality of DDR2-SDRAMs are arranged relative to an LSI (Large Scale Integration) having a memory interface loaded thereon, more specifically, in case the DDR2-SDRAMs are arranged at a distal end and at a proximal end of the LSI, the delay value of a data strobe signal (DQS) is to be adjusted separately. However, it is not shown that, in case a plurality of DDR2-SDRAMs are arranged at the proximal end or at the distal end of the LSI, training of the data strobe signal DSQ is to be carried out for each of the DDR2-SDRAMs.
Patent Literature 2 shows a memory module including a plurality memory ranks. However, it is completely silent about training the data strobe signal. On the other hand, Patent Literature 2 shows training the ODT signal. However, the ODT signal is supplied in common to the plurality of memory ranks, while it is not shown that training of the ODT signal is to be carried out separately for respective memories of the same rank group.